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Mixed-Signal Front End for Broadband Applications AD9878
FEATURES
Low cost 3.3 V CMOS MxFETM for broadband applications DOCSIS, EURO-DOCSIS, DVB, DAVIC compliant 232 MHz quadrature digital upconverter 12-bit direct IF DAC (TxDAC+TM) Up to 65 MHz carrier frequency DDS Programmable sampling clock rates Analog Tx output level adjust Dual 12-bit, 29 MSPS direct IF ADCs with video clamp input 10-bit, 29 MSPS sampling ADC 8-bit sigma-delta auxiliary DAC Direct interface to AD8321/AD8323 or AD8322/AD8327 PGA cable driver
FUNCTIONAL BLOCK DIAGRAM
I Tx D A TA Tx Q 16 SIN C - 1 12 DAC Tx
DDS - SPO R T 4 C ON TR O L R EGISTER S 3 - _ OU T C A IN T MC L K PLL IF1 0 [4 :0 ] MU X 10 ADC OSC IN Rx10
12
ADC
MU X - C LA MP L EVEL
Rx12B VID EO
IF1 2 [1 1 :0 ]
MU X MU X ADC
12
APPLICATIONS
Cable set-top boxes Cable and wireless modems
FL A G[2 :1 ]
Rx12A
03277- 0- 001
Figure 1. Functional Block Diagram
GENERAL DESCRIPTION
The AD9878 is a single-supply cable modem/set-top box mixed-signal front end. The device contains a transmit path interpolation filter, a complete quadrature digital upconverter, and transmit DAC. The receive path contains dual 12-bit ADCs and a 10-bit ADC. All internally required clocks and an output system clock are generated by the PLL from a single crystal oscillator or clock input. The transmit path interpolation filter provides an upsampling factor of 16x with an output signal bandwidth up to 5.8 MHz. Carrier frequencies up to 65 MHz with 26 bits of frequency tuning resolution can be generated by the direct digital synthesizer (DDS). The transmit DAC resolution is 12 bits and can run at sampling rates as high as 232 MSPS. Analog output scaling from 0 dB to 7.5 dB in 0.5 dB steps is available to preserve SNR when reduced output levels are required. The 12-bit ADCs provide excellent undersampling performance, allowing this device to deliver better than 10 ENOBs with IF inputs up to 70 MHz. The 12-bit IF ADCs can sample at rates up to 29 MHz, allowing them to process wideband signals. The AD9878 includes a programmable sigma-delta DAC, which can be used to control an external component such as a variable gain amplifier (VGA) or a voltage controlled tuner. The AD9878 also integrates a CA port that enables a host processor to interface with the AD8321/AD8323 or AD8322/AD8327/AD8328 programmable gain amplifier (PGA) cable drivers via the MxFE serial port (SPORT). The AD9878 is available in a 100-lead LQFP package. The AD9878 is specified over the extended industrial (-40C to +85C) temperature range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD9878
TABLE OF CONTENTS
SPECIFICATIONS ........................................................................... 3 ABSOLUTE MAXIMUM RATINGS............................................. 6 DEFINITIONS OF SPECIFICATIONS......................................... 7 TYPICAL PERFORMANCE CHARACTERISTICS ................... 8 REGISTER BIT DEFINITIONS ................................................... 11 SERIAL INTERFACE FOR REGISTER CONTROL ................. 15 GENERAL OPERATION OF THE SERIAL INTERFACE... 15 INSTRUCTION BYTE .............................................................. 15 SERIAL INTERFACE PORT PIN DESCRIPTION ............... 15 MSB/LSB TRANSFERS ............................................................. 16 NOTES ON SERIAL PORT OPERATION ............................. 16 THEORY OF OPERATION.......................................................... 17 TRANSMIT PATH..................................................................... 18 INTERPOLATION FILTER ..................................................... 18 DIGITAL UPCONVERTER ..................................................... 19 CLOCK AND OSCILLATOR CIRCUITRY........................... 21 PROGRAMMABLE CLOCK OUTPUT REFCLK................ 22 RESET AND TRANSMIT POWER-DOWN ......................... 23 RECEIVE PATH (Rx) ................................................................ 24 PCB DESIGN CONSIDERATIONS ........................................ 25 PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIOINS ........................................................................... 27 OUTLINE DIMENSIONS ............................................................ 34 ORDERING GUIDE.................................................................. 34
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 36
AD9878
SPECIFICATIONS
Table 1. ELECTRICAL CHARACTERISTICS
(VAS = 3.3 V 5%, VDS = 3.3 V 10%, fOSCIN = 27 MHz, fSYSCLK = 216 MHz, fMCLK = 54 MHz (M = 8), ADC Clock Derived from OSCIN, RSET = 4.02 k, Max. Fine Gain, 75 DAC Load.)
PARAMETER OSCIN and XTAL CHARACTERISTICS Frequency Range Duty Cycle Input Impedance MCLK Cycle to Cycle Jitter (fMCLK derived from PLL) Tx DAC CHARACTERISTICS Maximum Sample Rate Resolution Full-Scale Output Current Gain Error (Using Internal Reference) Offset Error Reference Voltage (REFIO Level) Differential Nonlinearity (DNL) Integral Nonlinearity (INL) Output Capacitance Phase Noise @ 1 kHz Offset, 42 MHz Carrier Output Voltage Compliance Range Wideband SFDR 5 MHz Analog Out, IOUT = 10 mA 65 MHz Analog Out, IOUT = 10 mA Narrow-Band SFDR (1 MHz Window) 5 MHz Analog Out, IOUT = 10 mA 65 MHz Analog Out, IOUT = 10 mA Tx MODULATOR CHARACTERISTICS I/Q Offset Pass-Band Amplitude Ripple (f < fIQCLK/8) Pass-Band Amplitude Ripple (f < fIQCLK/4) Stop-Band Response (f > fIQCLK x 3/4) Tx GAIN CONTROL Gain Step Size Gain Step Error Settling Time, 1% (Full-Scale Step) 10-BIT ADC CHARACTERISTICS Resolution Maximum Conversion Rate Pipeline Delay Analog Input Input Voltage Range Differential Input Impedance Full Power Bandwidth Dynamic Performance (f = 5 MHz) Signal-to-Noise and Distortion (SINAD) Effective Number of Bits (ENOB) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Reference Voltage Error, REFT10-REFB10 (1.0 V) Temp Full 25C 25C 25C Full N/A Full Full 25C 25C 25C 25C 25C 25C Full Full Full Full Full Full Full Full Full 25C 25C 25C N/A Full N/A Full 25C 25C Full Full Full Full Full Test Level II II III III II N/A II II III III III III III III II I I I I II II II II III III III N/A II N/A II III III I I I I I 57.6 9.2 65.7 Min 3 35 Typ Max 29 65 Unit MHz % M||pF ps rms MHz Bits mA % FS % FS V LSB LSB pF dBc/Hz V dB dB dB dB dB dB dB dB dB dB s Bits MHz ADC cycles Vppd k||pF MHz dB Bits dB dB mV
50 100||3 6
232 4 -2.5 12 10 -1 1.0 1.23 2.5 8 5 -110 20 +2.5
-0.5 62.4 50.3 71 61 50 68 53.5 74 64 55
+1.5
0.1 0.5 -63 0.5 <0.05 1.8 10 29 4.5 2 4||2 90 59.7 9.6 -71.1 72.4 4
-63.6 200
Rev. 0 | Page 3 of 36
AD9878
PARAMETER Dynamic Performance (f = 50 MHz) Signal-to-Noise and Distortion (SINAD) Effective Number of Bits (ENOB) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) 12-BIT ADC CHARACTERISTICS Resolution Maximum Conversion Rate Pipeline Delay Analog Input Input Voltage Range Differential Input Impedance Aperture Delay Aperture Uncertainty (Jitter) Full Power Bandwidth Input Referred Noise Reference Voltage Error, REFT12-REFB12 (1 V) Dynamic Performance (AIN = -0.5 dBFS, f = 5 MHz)
ADC Sample Clock = OSCIN
Temp Full Full Full Full N/A Full N/A Full 25C 25C 25C 25C 25C Full
Test Level I I I I N/A II N/A III III III III III III I
Min 54.8 8.8 56.9
Typ 57.8 9.3 -63.3 63.7 12
Max
Unit dB Bits dB dB Bits MHz ADC cycles Vppd k||pF ns ps rms MHz V mV
-56.9
29 5.5 2 4||2 2.0 1.2 85 75 16
-200
+200
Signal-to-Noise and Distortion (SINAD) Effective Number of Bits (ENOBs) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR)
ADC Sample Clock = PLL
Full Full Full Full Full Full Full Full Full Full
I I I I I II II II II II
61.0 9.8 64.2 62.8 60.4 9.74 62.4 62.7
67 10.8 66 -72.7 74.6 64.4 10.4 65.1 -72.7 74.6
-61.7
dB Bits dB dB dB dB Bits dB dB dB
Signal-to-Noise and Distortion (SINAD) Effective Number of Bits (ENOBs) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Dynamic Performance (AIN = -0.5 dBFS, f = 50 MHz)
ADC Sample Clock = OSCIN
-61.8
Signal-to-Noise and Distortion (SINAD) Effective Number of Bits (ENOB) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Differential Phase Differential Gain VIDEO ADC PERFORMANCE (f = 5 MHz)
ADC Sample Clock = OSCIN
Full Full Full Full Full 25C 25C
II II II II II III III
59.4 9.5 61.6 62.5
62.9 10.1 63.7 -71.7 72 <0.1 <1
-61.5
dB Bits dB dB dB Degrees LSB
Signal-to-Noise and Distortion (SINAD) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR)
Full Full Full Full
II II II II
46.7 54.3 45.9
53 63.2 -50.2 50
-45.9
dB Bits dB dB
Rev. 0 | Page 4 of 36
AD9878
PARAMETER CHANNEL-TO-CHANNEL ISOLATION Tx DAC-to-ADC Isolation (5 MHz Analog Output) Isolation between Tx and 10-Bit ADC Isolation between Tx and 12-Bit ADCs ADC-to-ADC Isolation (AIN = -0.5 dBFS, f = 5 MHz) Isolation between IF10 and IF12A/B Isolation between IF12A and IF12B TIMING CHARACTERISTICS (10 pF LOAD) Wake-Up Time Minimum RESET Pulsewidth Low (tRL) Digital Output Rise/Fall Time Tx/Rx Interface MCLK Frequency (fMCLK) TxSYNC/TxIQ Setup Time (tSU) TxSYNC/TxIQ Hold Time (tHD) MCLK Rising Edge to RxSYNC Valid Delay (tMD) OSCOUT Rising or Falling Edge to RxSYNC Valid Delay (tOD) OSCOUT Edge to MCLK Falling Edge (tEE) SERIAL CONTROL BUS Maximum SCLK Frequency (fSCLK) Minimum Clock Pulsewidth High (tPWH) Minimum Clock Pulsewidth Low (tPWL) Maximum Clock Rise/Fall Time Minimum Data/Chip-Select Setup Time (tDS) Minimum Data Hold Time (tDH) Maximum Data Valid Time (tDV) CMOS LOGIC INPUTS Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current Input Capacitance CMOS LOGIC OUTPUTS (1 mA Load) Logic "1" Voltage Logic "0" Voltage POWER SUPPLY Supply Current, IS (Full Operation) Analog Supply Current IAS Digital Supply Current IDS Supply Current, IS Standby (PWRDN Pin Active) Full Power-Down (Register 02 = 0xFF) Power-Down Tx Path (Register 02 = 0x60) Power-Down IF12 Rx Paths (Register 02 = 0x1B) Power Supply Rejection (Differential Signal) Tx DAC 10-Bit ADC 12-Bit ADC Temp Test Level Min Typ Max Unit
25C 25C
III III
>60 >80
dB dB
25C 25C N/A N/A Full Full Full Full Full Full Full Full Full Full Full Full Full Full 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C
III III N/A N/A II II II II II II II II II II II II II II II II II II III II II II III III II III III III III III III
>85 >85 200 5 2.8 4 66 3 3 0 TOSC/4 - 2.0 -1.0
dB dB TMCLK cycles tMCLK cycles ns MHz ns ns ns ns ns MHz ns ns s ns ns ns V V A A pF V V mA mA mA mA mA mA mA % FS % FS % FS
1.0 TOSC/4 + 3.0 +1.0 15
30 30 1 25 0 30 VDRVDD - 0.7 0.4 12 12 3 VDRVDD - 0.6 0.4 184 105 79 46 46 124 131 <0.25 <0.0001 <0.0004 204 115 89 53 52 159
Rev. 0 | Page 5 of 36
AD9878
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Power Supply (VAVDD, VDVDD, VDRVDD) Digital Output Current Digital Inputs Analog Inputs Operating Temperature Maximum Junction Temperature Storage Temperature Lead Temperature (Soldering 10 sec) Rating 3.9 V 5 mA -0.3 V to VDRVDD + 0.3 V -0.3 V to VAVDD + 0.3 V -40C to +85C 150C -65C to +150C 300C
EXPLANATION OF TEST LEVELS
I. Devices are 100% production tested at 25C and guaranteed by design and characterization testing for industrial operating temperature range (-40C to +85C). II. Parameter is guaranteed by design and/or characterization testing. III. Parameter is a typical value only. N/A. Test level definition is not applicable.
Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance: 100-Lead LQFP: JA = 40.5C/W
Rev. 0 | Page 6 of 36
AD9878
DEFINITIONS OF SPECIFICATIONS
Differential Nonlinearity Error (DNL, No Missing Codes) An ideal converter exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 10-bit resolution indicates that all 1,024 codes, respectively, must be present over all operating ranges. Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 11/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Phase Noise Single-sideband phase noise power is specified relative to the carrier (dBc/Hz) at a given frequency offset (1 kHz) from the carrier. Phase noise can be measured directly in single-tone transmit mode with a spectrum analyzer that supports noise marker measurements. It detects the relative power between the carrier and the offset (1 kHz) sideband noise and takes the resolution bandwidth (rbw) into account by subtracting 10 x log(rbw). It also adds a correction factor that compensates for the implementation of the resolution bandwidth, log display, and detector characteristic. Output Compliance Range The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. Spurious-Free Dynamic Range (SFDR) The difference, in dB, between the rms amplitude of the DAC's output signal (or ADC's input signal) and the peak spurious signal over the specified bandwidth (Nyquist bandwidth, unless otherwise noted). Pipeline Delay (Latency) The number of clock cycles between conversion initiation and the associated output data being made available. Offset Error The first code transition should occur at an analog value 1/2 LSB above negative full scale. Offset error is defined as the deviation of the actual transition from that point. Gain Error The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur for an analog value 11/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Aperture Delay The aperture delay is a measure of the Sample-and-Hold Amplifier (SHA) performance that specifies the time delay between the rising edge of the sampling clock input to when the input signal is held for conversion. Aperture Uncertainty (Jitter) Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the ADC. Input Referred Noise The rms output noise is measured using histogram techniques. The ADC output codes' standard deviation is calculated in LSB, and converted to an equivalent voltage. This results in a noise figure that can be directly referred to the input of the MxFE. Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. Effective Number of Bits (ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, it is possible to get a measure of performance expressed as N, the effective number of bits: N = (SINAD - 1.76)dB/6.02 Thus, the effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal, and is expressed as a percentage or in decibels. Power Supply Rejection Power supply rejection specifies the converter's maximum fullscale change when the supplies are varied from nominal to minimum and maximum specified voltages. Channel-to-Channel Isolation (Crosstalk) In an ideal multichannel system, the signal in one channel will not influence the signal level of another channel. The channelto-channel isolation specification is a measure of the change that occurs in a grounded channel as a full-scale signal is applied to another channel.
Rev. 0 | Page 7 of 36
AD9878
TYPICAL PERFORMANCE CHARACTERISTICS
0 -10 -20 -30 MAGNITUDE - dB MAGNITUDE - dB -40 -50 -60 -70 -80 -90 -100 0 2 4 6 8 10 12 14 FREQUENCY - MHz 16 18 20
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 55 57 59 61 63 65 67 69 FREQUENCY - MHz 71 73 75
03277- 0- 022
03277- 0- 025
Figure 2. Dual Sideband Spectral Plot, fC = 5 MHz, f = 1 MHz, RSET =10 k (IOUT = 4 mA), RBW = 1 kHz
0 -10 -20 -30 MAGNITUDE - dB
Figure 5. Dual Sideband Spectral Plot, fC = 65 MHz, f = 1 MHz, RSET = 4 k (IOUT = 10 mA), RBW = 1 kHz
0 -10 -20 -30
MAGNITUDE - dB
-40 -50 -60 -70 -80 -90 -100 0 2 4 6 8 10 12 14 FREQUENCY - MHz 16 18 20
-40 -50 -60 -70 -80 -90 -100 0 20 40 60 80 FREQUENCY - MHz 100 120
03277- 0- 026
03277- 0- 023
Figure 3. Dual Sideband Spectral Plot, fC = 5 MHz, f = 1 MHz, RSET = 4 k (IOUT = 10 mA), RBW=1 kHz
0 -10 -20 -30
MAGNITUDE - dB
Figure 6. Single Sideband @ 65 MHz, RBW = 2 kHz, fC = 66 MHz, f = 1 MHz, RSET = 10 k (IOUT = 4 mA)
0 -10 -20 -30
MAGNITUDE - dB
-40 -50 -60 -70 -80 -90 -100 55 57 59 61 63 65 67 69 FREQUENCY - MHz 70 73 75
-40 -50 -60 -70 -80 -90 -100 0 20 40 60 80 FREQUENCY - MHz 100 120
03277- 0- 027
03277- 0- 024
Figure 4. Dual Sideband Spectral Plot, fC = 65 MHz, f = 1 MHz, RSET =10 k (IOUT = 4 mA), RBW = 1 kHz
Figure 7. Single Sideband @ 65 MHz, RBW = 2 kHz, fC = 66 MHz, f = 1 MHz, RSET = 4 k (IOUT = 10 mA)
Rev. 0 | Page 8 of 36
AD9878
0 -10 -20 -30
MAGNITUDE - dB
0 -10 -20
MAGNITUDE - dB
-30 -40 -50 -60 -70 -80 -90
-40 -50 -60 -70 -80 -90 -100 0 20 40 60 80 FREQUENCY - MHz 100 120
03277- 0- 028
0
20
40 60 80 FREQUENCY - MHz
100
120
03277- 0- 031
Figure 8. Single Sideband @ 42 MHz, RBW = 2 kHz ,fC = 43 MHz, f = 1 MHz, RSET = 10 k (IOUT = 4 mA)
Figure 11. Single Sideband @ 5 MHz, RBW = 2 kHz, fC = 6 MHz, f = 1 MHz, RSET = 4 k (IOUT = 10 mA)
0 -10 -20
MAGNITUDE - dB
0 -10 -20
MAGNITUDE - dB
-30 -40 -50 -60 -70 -80 -90
-30 -40 -50 -60 -70 -80 -90 -2.5
0
20
40 60 80 FREQUENCY - MHz
100
120
03277- 0- 029
-2.0
-1.5
-1.0
-0.5 0 0.5 1.0 FREQUENCY - MHz
1.5
2.0
2.5
03277- 0- 032
Figure 9. Single Sideband @ 42 MHz, RBW = 2 kHz, fC = 43 MHz, f = 1 MHz, RSET = 4 k (IOUT = 10 mA)
Figure 12. Single Sideband @ 65 MHz, RBW = 500 Hz, fC = 66 MHz, f = 1 MHz, RSET = 10 k (IOUT = 4 mA)
0 -10 -20 -30
MAGNITUDE - dB
0 -10 -20
MAGNITUDE - dB
-30 -40 -50 -60 -70 -80 -90 -2.5
-40 -50 -60 -70 -80 -90 -100 0 20 40 60 80 FREQUENCY - MHz 100 120
03277- 0- 030
-2.0
-1.5
-1.0
-0.5 0 0.5 1.0 FREQUENCY - MHz
1.5
2.0
2.5
03277- 0- 033
Figure 10. Single Sideband @ 5 MHz, RBW = 2 kHz, fC = 6 MHz, f = 1 MHz, RSET = 10 k (IOUT = 4 mA)
Figure 13. Single Sideband @ 65 MHz, RBW = 500 Hz, fC = 66 MHz, f = 1 MHz, RSET = 4 k (IOUT = 10 mA)
Rev. 0 | Page 9 of 36
AD9878
0 -10 -20 -20 -30
MAGNITUDE - dB MAGNITUDE - dB
0 -10
-40 -50 -60 -70 -80 -90 -100 -50 -40 -30 -20 -10 0 10 20 FREQUENCY - MHz 30 40 50
-30 -40 -50 -60 -70 -80
0
5
10
15
03277- 0- 034
20 25 30 35 FREQUENCY - MHz
40
45
50
03277- 0- 036
Figure 14. Single Sideband @ 65 MHz, RBW = 50 Hz, fC = 66 MHz, f = 1 MHz, RSET = 10 k (IOUT = 4 mA)
Figure 16. 16-QAM @ 42 MHz Spectral Plot, RBW = 1 kHz
0 -10 -20
0 -10 -20
-30
MAGNITUDE - dB
MAGNITUDE - dB
-40 -50 -60 -70 -80 -90 -100 -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 FREQUENCY - MHz 1.5 2.0 2.5
-30 -40 -50 -60 -70 -80
0
5
10
15
03277- 0- 035
20 25 30 35 FREQUENCY - MHz
40
45
50
03277- 0- 037
Figure 15. Single Sideband @ 65 MHz, RBW = 10 Hz, fC = 66 MHz, f = 1 MHz, RSET = 10 k (IOUT = 4 mA)
Figure 17. 16-QAM @ 5 MHz Spectral Plot, RBW = 1 kHz
Rev. 0 | Page 10 of 36
AD9878
REGISTER BIT DEFINITIONS
Table 3. AD9878 Register Map
Address (hex) 00 Bit 7 SDIO Bidirectional PLL Lock Detect Power Down PLL Power Down DAC Tx Power Down Digital Tx Video Input into ADC12B Flag 0 Power Down ADC12A Flag 2 Sigma-Delta Output Control Word [7:0] Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 OSC IN Multiplier M[4:0] MCLK Divider R[5:0] Power Down ADC12B Power Down ADC10 Power Down Reference ADC12A Flag 1 Power Down Reference ADC12B Flag 0 Enable Bit 1 Bit 0 Default (hex) Type
LSB First
Reset
0x08 0x00 0x00 0x00 0x00 0x00 0x00
Read/Write
01
Read/Write
02 03 04 05 06 07 08
Read/Write Read/Write Read/Write Read/Write Read-Only Read/Write Read/Write
Video Input Enable ADC Clocked Direct from OSCIN Rx Port Fast Edge Rate
Clamp Level for Vidio Input [6:0] Power Down Rx Sync Gen Power-Down Reference ADC10 Send ADC12A Data Only Send ADC12B Data Only
0x00 0x80 0x00 0x00 0x00
Version [3:0]
09
Read/Write
0A 0B 0C 0D 0E 0F Tx Path Select Profile 1 Tx Path AD8321/3 Gain Control Mode
Read/Write
Read/Write Read/Write Read/Write Read/Write Read/Write
0x00 0x00 0x00
Tx Path Transmit Single Tone
Tx Frequency Tuning Word Profile 1 LSBs [1:0]
Tx Frequency Tuning Word Profile 0 LSBs [1:0]
DAC Fine Gain Control [3:0] Tx Path Bypass sinc-1 Filter Tx Path Spectral Inversion
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
10 11 12 13 14 15 16 17
Tx Path Frequency Tuning Word Profile 0 [9:2] Tx Path Frequency Tunin g Word Profile 0 [17:10] Tx Path Frequency Tuning Word Profile 0 [25:18] Cable Driver Amplifier Coarse Gain Control Profile 0 [7:4] Fine Gain Control Profile 0 [3:0]
Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write
Tx Path Frequency Tu ning Word Profile 1 [9:2] Tx Path Frequency Tuning Word Profile 1 [17:10] Tx Path Frequency Tuning Word Profile 1 [25:18] Cable Driver Amplifier Coarse Gain Control Profile 1 [7:4] Fine Gain Control Profile 1 [3:0]
REGISTER 0--INITIALIZATION
Bits 0 to 4: OSCIN Multiplier
This register field is used to program the on-chip multiplier (PLL) that generates the chip's high frequency system clock, fSYSCLK. For example, to multiply the external crystal clock fOSCIN by 16 decimal, program Register 0, Bits 4:0 as 0x10. The default value of M is 0x08. Valid entries range from 1 to 31. When M is chosen equal to 1, the PLL is disabled and all internal clocks are derived directly from OSCIN. The PLL requires 200 MCLK cycles to regain frequency lock after a change in M, the clock multiplier value. After the recapture time of the PLL, the frequency of fSYSCLK is stable.
Rev. 0 | Page 11 of 36
AD9878
Bit 5: Reset
Writing a 1 to this bit resets the registers to their default values and restarts the chip. The Reset bit always reads back 0. The bits in Register 0 are not affected by this software reset. However, a low level at the RESET pin would force all registers, including all bits in Register 0, to their default state.
Bit 2: Power-Down ADC10
Active high powers down the 10-bit ADC.
Bit 3: Power-Down ADC12B
Active high powers down the ADC12B.
Bit 6: LSB First
Active high indicates SPI serial port access of instruction byte and data registers is least significant bit (LSB) first. Default low indicates most significant bit (MSB) first format.
Bit 4: Power-Down ADC12A
Active high powers down the ADC12A.
Bit 5: Power-Down Tx
Active high powers down the digital transmit section of the chip, similar to the function of the PWRDN pin.
Bit 7: SDIO Bidirectional
Active high configures the serial port as a three signal port with the SDIO pin used as a bidirectional input/output pin. Default low indicates the serial port uses four signals with SDIO configured as an input and SDO configured as an output.
Bit 6: Power-Down DAC Tx
Active high powers down the DAC.
Bit 7: Power-Down PLL
REGISTER 1--CLOCK CONFIGURATION
Bits [5:0]: MCLK Divider.
This register determines the output clock on the OSCOUT pin. At default 0 (R = 0), OSCOUT provides a buffered version of the OSCIN clock signal for other chips. The register can also be used to divide the chip's master clock fMCLK by R, where R is an integer number between 2 and 63. The generated reference clock on OSCOUT pin can be used for external frequency controlled devices.
Active high powers down the OSCIN multiplier.
REGISTER 3--FLAG CONTROL
Bit 0: Flag 0 Enable
Active high, the SDELTA pin will maintain a fixed logic level determined directly by the MSB of the sigma-delta control word of Register 4.
Bit 1: Flag 1
The logic level of this bit will be applied at the FLAG1 pin.
Bit 7: PLL Lock Detect
When this bit is set low, the OSCOUT pin functions in its default mode and provides an output clock with frequency fMCKL/R as described above. If this bit is set to 1, the OSCOUT pin is configured to indicate whether the PLL is locked to fOSCIN. In this mode the OSCOUT pin should be low-pass filtered with an RC filter of 1.0 k and 0.1 F. A high output on OSCOUT indicates that the PLL has achieved lock with fOSCIN.
Bit 4: Flag 2
The logic level of this bit will be applied at the FLAG2 pin.
Bit 5: Video Input into ADC12B
If the video input is enabled, setting this bit high sends the signal applied to the VIDEO IN pin to the ADC12B. Otherwise, the signal applied to the VIDEO IN pin is sent to the ADC12A.
REGISTER 2--POWER-DOWN
Sections of the chip that are not used can be powered down when the corresponding bits are set high. This register has a default value of 0x00; all sections active.
REGISTER 4--SIGMA-DELTA CONTROL WORD
Bits [7:0]: Sigma-Delta Control Word
The sigma-delta control word is 8 bits wide and controls the duty cycle of the digital output on the SIGDELT pin. Changes to the sigma-delta control word take effect immediately for every register write. Sigma-delta output control words have a default value of 0. The control words are in straight binary format with 0x00 corresponding to the bottom of scale or 0% duty cycle, and 0xFF corresponding to the top of scale or near 100% duty cycle.
Bit 0: Power-Down ADC 12B Voltage Reference
Active high powers down the voltage reference circuit for ADC12B.
Bit 1: Power-Down ADC12A Voltage Reference
Active high powers down the voltage reference circuit for ADC12A.
Rev. 0 | Page 12 of 36
AD9878
Bit 7: Flag 0 (Sigma-Delta Control Word MSB)
When the Flag 0 Enable bit (Register 3, Bit 0) is set, the logic level of this bit will appear on the output of the SIGDELT pin.
Bit 7: ADC Clocked Directly from OSCIN
When set high, the ADC sampling clock is derived directly from the input clock at OSCIN. In this mode, the clock supplied to the OSCIN pin should originate from an external crystal or low jitter crystal oscillator. When this bit is low, the ADC sampling clock is derived from the internal PLL and the frequency of the clock is equal to fOSCIN x M/8.
REGISTER 07--VIDEO INPUT CONFIGURATION
Bits [6:0]: Clamp Level Control Value
The 7-bit clamp level control value is used to set an offset to the automatic clamp level control loop. The actual ADC output will have a clamp level offset equal to 16 times the clamp level control value as shown:
REGISTER C--DIE REVISION
Bits [3:0]: Version
The die version of the chip can be read from this register.
Clamp Level Offset Clamp Level Control Value = (x)16
The default value for the clamp level control value is 0x20. This results in an ADC output clamp level offset of 512 LSBs. The valid programming range for the clamp level control value is from 0x16 to 0x127.
REGISTER D--Tx FREQUENCY TUNING WORDS LSBS
This register accommodates the two least significant bits each for both of the frequency tuning words. See the description of the burst parameter below.
REGISTER 8--ADC CLOCK CONFIGURATION
Bit 0: Send ADC12B Data Only
When this bit is set high, the device enters a nonmultiplexed mode and only the data from the ADC12B will be sent to the IF[11:0] digital output port.
REGISTER E--DAC GAIN CONTROL
This register allows the user to program the DAC gain if the TxGain Control Select Bit 3 in Register F is set to 0.
Bits [3:0] 0000 0001 0010 0011 ... 1110 1111 DAC Gain (dB) 0.0 (default) 0.5 1.0 1.5 ... 7.0 7.5
Bit 1: Send ADC12A Data Only
When this bit is set high, the device enters a nonmultiplexed mode and only the data from the ADC12A will be sent to the IF[11:0] digital output port. Note: If both the Send ADC12B Data Only and Send ADC12A Data Only register bits are set high, the device will send both ADC12A and ADC12B data in multiplexed mode.
REGISTER F--Tx PATH CONFIGURATION
Bit 0: Single Tone Tx Mode
Active high configures the AD9878 for single-tone applications (e.g., FSK). The AD9878 will supply a single frequency output as determined by the frequency tuning word selected by the active profile. In this mode, the TxIQ input data pins are ignored but should be tied to a valid logic voltage level. Default value is 0 (inactive).
Bit 3: Power-Down ADC10 Voltage Reference
Active high powers down the voltage reference circuit for ADC10.
Bit 4: Power Down RxSYNC Generator
Setting this bit to 1 powers down the 10-bit ADC's sampling clock and makes the RxSYNC output pin stay low. It can be used for additional power saving on top of the power-down selections in Register 2.
Bit 1: Spectral Inversion Tx
When set to 1, inverted modulation is performed:
Bit 5: Rx PORT Fast Edge Rate
Setting this bit to 1 increases the output drive strength of all digital output pins except MCLK, REFCLK, SIGDELT, and FLAG[2:1]. These pins always have high output drive capability.
MODULATOR_OUT = [I cos (t) + Q sin (t)].
Default is logic 0, non-inverted modulation:
MODULATOR_OUT = [I cos (t) - Q sin (t)].
Rev. 0 | Page 13 of 36
AD9878
Bit 2: Bypass Inv Sinc Tx Filter
Active high, configures the AD9878 to bypass the sin(x)/x compensation filter. Default value is 0 (inverse sinc filter enabled). default mode, the complete 8-bit register value is transmitted over the 3-wire cable amplifier (CA) interface. If Bit 3 of Register F is set high, Bits [7:4] of Registers 0x13 and 0x17 will determine the 8-bit word sent over the CA interface according to the table below:
Bits [7:4] 0000 0001 0010 0011 0100 0101 0110 0111 1000 CA Interface Transmit Word 0000 0000 (default) 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000
Bit 3: CA Interface Mode Select
This bit changes the manner in which transmit gain control is performed. Typically either AD8321/AD8323 (default 0) or AD8322/AD8327 (1) variable gain cable amplifiers are programmed over the chip's 3-wire CA interface. The Tx Gain Control Select changes the interpretation of the bits in Registers 13, 17, 1B, and 1F. See the Cable Driver Gain Control section below.
Bit 5: Profile Select
The AD9878 quadrature digital upconverter is capable of storing two preconfigured modulation modes called profiles. Each profile defines a transmit frequency tuning word and cable driver amplifier gain (/DAC gain) setting. The Profile Select bit or PROFILE pin programs the current register profile to be used. The Profile Select bit should always be 0 if the PROFILE pin is used to switch between profiles. Using the Profile Select bit as a means of switching between different profiles requires the PROFILE pin to be tied low.
In this mode the lower bits of Registers 0x13 and 0x17 determine the fine gain setting of the DAC output:
Bits [3:0] 0000 0001 0010 0011 ... 1110 1111 DAC Fine Gain (dB) 0.0 (default) 0.5 1.0 1.5 ... 7.0 7.5
REGISTERS 10 THROUGH 17: BURST PARAMETER
Tx Frequency Tuning Words
The frequency tuning word (FTW) determines the DDS generated carrier frequency (fC) and is formed via a concatenation of register addresses. The 26-bit FTW is spread over four register addresses. Bit 25 is the MSB and Bit 0 is the LSB. The carrier frequency equation is given as:
New data is automatically sent over the 3-wire CA interface (and DAC gain adjust) whenever the value of the active gain control register changes or a new profile is selected. The default value is 0x00 (lowest gain). The formula for the combined output level calculation of AD9878 fine gain and AD8327 or AD8322 coarse gain is:
V8327 = V9878(0) + (fine)/2 + (coarse) - 19 V8322 = V9878(0) + (fine)/2 + (coarse) - 14
where:
fC = (FTW x fSYSCLK)/226
where :
fine = decimal value of Bits [3:0] coarse = decimal value of Bits [7:4] V9878(0): Level at AD9878 output in dBmV for fine = 0. V8327: Level at output of AD8327 in dBmV. V8322: Level at output of AD8322 in dBmV.
fSYSCLK = M x fOSCIN , and FTW < 0x2000
Changes to FTW bytes take effect immediately.
Cable Driver Gain Control
The AD9878 has a 3-pin interface to the AD832x family of programmable gain cable driver amplifiers. This allows direct control of the cable driver's gain through the AD9878. In its
Rev. 0 | Page 14 of 36
AD9878
SERIAL INTERFACE FOR REGISTER CONTROL
The AD9878 serial port is a flexible, synchronous serial communications port that allows easy interface to many industry standard microcontrollers and microprocessors. The interface allows read/write access to all registers that configure the AD9878. Single or multiple byte transfers are supported. Also, the interface can be programmed to read words either MSB first or LSB first. The AD9878's serial interface port I/O can be configured to have one bidirectional I/O (SDIO) pin or two unidirectional I/O (SDIO/SDO) pins.
Table 4.
N1 0 0 1 1 N0 0 1 0 1 Description Transfer 1 Byte Transfer 2 Bytes Transfer 3 Bytes Transfer 4 Bytes
General Operation of the Serial Interface
There are two phases to a communication cycle with the AD9878. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9878, coincident with the first eight SCLK rising edges. The instruction byte provides the AD9878 serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9878. The eight remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9878 and the system controller. Phase 2 of the communication cycle is a transfer of 1 to 4 data bytes as determined by the instruction byte. Normally, using one multibyte transfer is the preferred method. However, single-byte data transfers are useful to reduce CPU overhead when register access requires one byte only. Registers change immediately upon writing to the last bit of each transfer byte.
The Bits [A4:A0] determine which register is accessed during the data transfer portion of the communications cycle. For multibyte transfers, this address is the starting byte address. The remaining register addresses are generated by the AD9878.
tDS
CS
tSCLK tPWH tPWL
SCLK
tDS
SDIO
tDH
INSTRUCTION BIT 6
03277- 0- 005
INSTRUCTION BIT 7
Figure 18. Timing Diagram for Register Write
CS SCLK
tDV
SDIO SDO DATA BIT N DATA BIT N
03277- 0- 006
Figure 19. Timing Diagram for Register Read
Serial Interface Port Pin Description
SCLK--Serial Clock. The serial clock pin is used to synchronize data transfers from the AD9878 and to run the serial port state machine. The maximum SCLK frequency is 15 MHz. Input data to the AD9878 is sampled on the rising edge of SCLK. Output data changes on the falling edge of SCLK. CS--Chip Select. Active low input starts and gates a
communication cycle. It allows multiple devices to share a common serial port bus. The SDO and SDIO pins go to a high impedance state when CS is high. Chip select should stay low during the entire communication cycle.
Instruction Byte
The instruction byte contains the following information:
MSB 17 R/W 16 N1 15 N0 14 A4 13 A3 12 A2 11 A1 LSB 10 A0
SDIO--Serial Data I/O. Data is always written into the AD9878
on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Bit 7 of Register 0. The default is Logic 0, which configures the SDIO pin as unidirectional.
The R/W bit of the instruction byte determines whether a read or a write data transfer will occur after the instruction byte write. Logic high indicates a read operation. Logic low indicates a write operation. The [N1:N0] bits determine the number of bytes to be transferred during the data transfer cycle. The bit decodes are shown in Table 4. The timing diagrams are shown in Figure 18 and Figure 19.
SDO--Serial Data Out. Data is read from this pin for protocols
that use separate lines for transmitting and receiving data. In the case where the AD9878 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state.
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AD9878
MSB/LSB Transfers
The AD9878 serial port can support most significant bit (MSB) first or least significant bit (LSB) first data formats (see Figure 20 and Figure 21). This functionality is controlled by the LSB First bit in Register 0. The default mode is MSB First. When this bit is set active high, the AD9878 serial port is in LSB First format. In LSB First mode, the instruction byte and data bytes must be written from the least significant bit to the most significant bit. In LSB First mode, the serial port internal byte address generator increments for each byte of the multibyte communication cycle.
CS SCLK SDIO SDO
R/W N1 N0 A4 A3 A2 A1 A0 D7n D6n D7n D6n D20 D10 D00 D20 D10 D00
03277- 0- 003
Notes on Serial Port Operation
The AD9878 serial port configuration bits reside in Bits 6 and 7 of Register Address 0x00. It is important to note that the configuration changes immediately upon writing to the last bit of the register. For multibyte transfers, writing to this register may occur during the middle of the communication cycle. Measures must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle. The same considerations apply when setting the Reset bit in Register Address 0x00. All other registers are set to their default values, but the software reset does not affect the bits in Register Address 0x00. It is recommended to use only single-byte transfers when changing serial port configurations or initiating a software reset. A write to Bits 1, 2, and 3 of Address 0x00 with the same logic levels as Bits 7, 6, and 5 (bit pattern: XY1001YX binary) allows the user to reprogram a lost serial port configuration and to reset the registers to their default values. A second write to Address 0x00 with the Reset bit low and the serial port configuration as specified above (XY), reprograms the OSCIN multiplier setting. A changed fSYSCLK frequency is stable after a maximum of 200 fMCLK cycles (wake-up time).
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
Figure 20. Serial Register Interface Timing, MSB First
CS SCLK SDIO SDO
A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20 D00 D10 D20 D6n D7n D6n D7n
03277- 0- 004
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
Figure 21. Serial Register Interface Timing, LSB First
When this bit is set default low, the AD9878 serial port is in MSB First format. In MSB First mode, the instruction byte and data bytes must be written from the most significant bit to the least significant bit. In MSB First mode, the serial port internal byte address generator decrements for each byte of the multibyte communication cycle. When incrementing from 0x1F, the address generator changes to 0x00. When decrementing from 0x00, the address generator changes to 0x1F.
Rev. 0 | Page 16 of 36
AD9878
THEORY OF OPERATION
For a general understanding of the AD9878, refer to Figure 22, a block diagram of the device architecture. The device consists of a transmit path, receive path, and auxiliary functions, such as a PLL, a sigma-delta DAC, a serial control port, and a cable amplifier interface. The transmit path contains an interpolation filter, a complete quadrature digital up-converter, an inverse sinc filter, and a 12-bit current output DAC. The receive path contains a 10-bit ADC and a dual 12-bit ADC. All internally required clocks and an output system clock are generated by the PLL from a single crystal or clock input. The 12-bit and 10-bit IF ADCs can convert direct IF inputs up to 70 MHz and run at sample rates up to 33 MSPS. A video input with an adjustable signal clamping level along with the 10-bit ADC allow the AD9878 to process an NTSC and a QAM channel simultaneously. The programmable sigma-delta DAC can be used to control external components, such as variable gain amplifiers (VGAs) or voltage controlled tuners. The CAPORT provides an interface to the AD8321/AD8323 or AD8322/AD8327 programmable gain amplifier (PGA) cable drivers, enabling host processor control via the MxFE serial port (SPORT).
AD9878
DATA ASSEMBLER TxIQ 6 I 12 FIR LPF 4 12 CIC LPF
QUADRATURE MODULATOR COS 4
DAC GAIN CONTROL SINC-1 BYPASS SINC-1 MUX 12 DAC
FSADJ
Tx
TxSYNC
Q
12
4
12
4 DDS
SIN
(fSYSCLK) (fOSCIN) PLL OSCIN x M XTAL
(fIQCLK) /4 MCLK REFCLK /R (fMCLK)
/4 - INPUT REG /8 12 -
OSCIN -_OUT
CA_PORT PROFILE SPORT
3
CA INTERFACE PROFILE SELECT
FLAG1 /2 (fOSCIN) /2 10 ADC F10 INPUT
4
SERIAL INTERFACE
IF10[4:0]
5
IF10
MUX
RxSYNC
Rx PORT
/2 (fOSCIN) 12 ADC MUX IF12B INPUT VIDEO INPUT 12
IF12[11:0]
12
IF12
MUX
ADC
MUX
IF12A INPUT
- CLAMP LEVEL
+ DAC
03277- 0- 007
Figure 22. AD9878 Block Diagram
Rev. 0 | Page 17 of 36
AD9878
tSU
MC L K
tHU
T x SYN C
Tx IQ
TxI [ 11: 6]
TxI [ 5: 0]
TxQ [ 11: 6]
TxQ [ 5: 0]
TxI [ 11: 6] '
TxI [ 5: 0] '
TxQ [ 11: 6] '
TxQ [ 5: 0] '
TxI [ 11: 6] ' '
TxI [ 5: 0] ' '
03277- 0-008
Figure 23. Tx Timing Diagram
Transmit Path
The transmit path contains an interpolation filter, a complete quadrature digital up-converter, an inverse sinc filter, and a 12-bit current output DAC. The maximum output current of the DAC is set by an external resistor. The Tx output PGA provides additional transmit signal level control. The transmit path interpolation filter provides an up-sampling factor of 16 with an output signal bandwidth as high as 5.8 MHz. Carrier frequencies up to 65 MHz with 26 bits of frequency tuning resolution can be generated by the direct digital synthesizer (DDS). The transmit DAC resolution is 12 bits and it can run at sampling rates up to 232 MSPS. Analog output scaling from 0 dB to 7.5 dB in 0.5 dB steps is available to preserve SNR when reduced output levels are required.
INTERPOLATION FILTER
Once through the Data Assembler, the IQ data streams are fed through a 4x FIR low-pass filter and a 4x Cascaded Integrator Comb (CIC) low-pass filter. The combination of these two filters results in the sample rate increasing by a factor of 16x. In addition to the sample rate increase, the half-band filters provide the low-pass filtering characteristic necessary to suppress the spectral images between the original sampling frequency and the new (16x higher) sampling frequency.
HALF-BAND FILTERS (HBFs)
HBF 1 and HBF 2 are both interpolating filters, each of which doubles the sampling rate. Together, HBF 1 and HBF 2 have 26 taps and provide a factor of four increase in the sampling rate (4 x fIQCLK or 8 x fNYQ). In relation to phase response, both HBFs are linear phase filters. As such, virtually no phase distortion is introduced within the pass band of the filters. This is an important feature, as phase distortion is generally intolerable in a data transmission system.
DATA ASSEMBLER
The AD9878 data path operates on two 12-bit words, the I and Q components, that form a complex symbol. The data assembler builds the 24-bit complex symbols from four consecutive 6-bit words read over the TxIQ [5:0] bus. These words are strobed into the data assembler synchronous to the master clock (MCLK). A high level on TxSYNC signals the start of a transmit symbol. The first two 6-bit words of the symbol form the I component; the second two 6-bit words form the Q component. Symbol components are assumed to be in twos complement format. The timing of the interface is fully described in the Transmit Timing section. The I/Q sample rate fIQCLK puts a bandwidth limit on the maximum transmit spectrum. This is the familiar Nyquist limit (hereafter referred to as fNYQ) and is equal to one-half fIQCLK.
CASCADED INTEGRATOR COMB (CIC) FILTER
The CIC filter is configured as a programmable interpolator and provides a sample rate increase by a factor of 4. The frequency response of the CIC filter is given by:
1 1-e H (f ) = 4
- j (2f ( 4 )) 3
1-e
j 2f
= 1 sin(4f ) 4 sin(f )
3
COMBINED FILTER RESPONSE
The combined frequency response of the HBF and CIC filters puts a limit on the input signal bandwidth that can be propagated through the AD9878.The usable bandwidth of the filter chain puts a limit on the maximum data rate that can be propagated through the AD9878. A look at the pass-band detail of the combined filter response (Figure 24) indicates that in order to maintain an amplitude error of no more than 1 dB, signal bandwidth is restricted to no more than about 60% of fNYQ. Thus, in order to keep the bandwidth of the data in the flat portion of the filter pass band, the user must oversample the
TRANSMIT TIMING
The AD9878 provides a master clock MCLK and expects 6-bit multiplexed TxIQ data on each rising edge (see Figure 23). Transmit symbols are framed with the TxSYNC input. TxSYNC high indicates the start of a transmit symbol. Four consecutive 6-bit data packages form a symbol (I MSB, I LSB, Q MSB, and Q LSB).
Rev. 0 | Page 18 of 36
AD9878
baseband data by at least a factor of two prior to presenting it to the AD9878. Note that without oversampling, the Nyquist bandwidth of the base-band data corresponds to fNYQ. As such, the upper end of the data bandwidth will suffer 6 dB or more of attenuation due to the frequency response of the digital filters. Furthermore, if the baseband data applied to the AD9878 has been pulse shaped, there is an additional concern. Typically, pulse shaping is applied to the baseband data via a filter having a raised cosine response. In such cases, an value is used to modify the bandwidth of the data where the value of is such that: 0 < < 1. A value of 0 causes the data bandwidth to correspond to the Nyquist bandwidth. A value of 1 causes the data bandwidth to be extended to twice the Nyquist bandwidth. Thus, with 2x oversampling of the baseband data and = 1, the Nyquist bandwidth of the data will correspond with the I/Q Nyquist bandwidth. As stated earlier, this results in problems near the upper edge of the data bandwidth due to the frequency response of the filters. The maximum value of that can be implemented is 0.45. This is because the data bandwidth becomes:
1 / 2 (1 + )f NYQ = 0.725f NYQ
DIGITAL UPCONVERTER
The digital quadrature modulator stage following the CIC filters is used to frequency shift (upconvert) the baseband spectrum of the incoming data stream up to the desired carrier frequency. The carrier frequency is controlled numerically by a direct digital synthesizer (DDS). The DDS uses the internal system clock (fSYSCLK) to generate the desired carrier frequency with a high degree of precision. The carrier is applied to the I and Q multipliers in quadrature fashion (90 phase offset) and summed to yield a data stream that is the modulated carrier. The modulated carrier becomes the 12-bit sample sent to the DAC.
Tx SIGNAL LEVEL CONSIDERATIONS
The quadrature modulator itself introduces a maximum gain of 3 dB in signal level. To visualize this, assume that both the I data and Q data are fixed at the maximum possible digital value, x. Then the output of the modulator, z, is
z = [x cos(t ) - x sin(t )]
Q X Z X I
which puts the data bandwidth at the extreme edge of the flat portion of the filter response.
03277- 0- 010
If a particular application requires an value between 0.45 and 1, then the user must oversample the baseband data by at least a factor of four. Over the frequency range of the data to be transmitted, the combined HB1, HB2, and CIC filter introduces a worst-case droop of less than 0.2 dB.
1 0 -1
MAGNITUDE - dB
Figure 25. 16-Quadrature Modulation
It can be shown that |z| assumes a maximum value of z = x 2 + x 2 = x 2 (a gain of +3 dB). However, if the same number of bits were used to represent the |z| values that were used to represent the x values, an overflow would occur. To prevent this possibility, an effective -3 dB attenuation is internally implemented on the I and Q data path:
z = 1/ 2 + 1/ 2 = x
-2 -3 -4 -5 -6
The following example assumes a PK/rms level of 10 dB:
Maximum Symbol Component Input Value = 2047 LSBs - 0.2 dB = 2000 LSBs Maximum Complex Input RMS Value =
2000 LSBs 6 dB - Pk rms (dB) = 1265 LSBs rms
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 FREQUENCY RELATIVE TO I/Q NYQ BW 0.9 1.0
03277- 0- 009
Figure 24. Cascaded Filter Pass Band
The maximum complex input rms value calculation uses both I and Q symbol components that add a factor of 2 (= 6 dB) to the formula. Table 5 shows typical I-Q input test signals with amplitude levels related to 12-bit full scale (FS).
Rev. 0 | Page 19 of 36
AD9878
Table 5. I-Q Input Test Signals
Analog Output Single Tone (fC - f) Single Tone (fC + f) Dual Tone (fC f) Modulator Output Input Level Level FS - 0.2 dB FS - 3.0 dB FS - 0.2 dB FS - 0.2 dB FS - 0.2 dB FS - 0.2 dB FS - 0.2 dB FS - 3.0 dB
then RSET = (39.4/0.02), or approximately 2 k. The following equation calculates the full-scale output current including the programmable DAC gain control.
Digital Input I = cos(f) Q = cos(f + 90) = -sin(f) I = cos(f) Q = cos(f + 270) = +sin(f) I = cos(f) FS - 0.2 dB FS Q = cos(f + 180) = -cos(f) or Q = +cos(f)
IOUT = 39.4/RSET x 10(-7.5 + 0.5NGAIN)/20
where NGAIN is the value of DAC Fine Gain Control[3:0]. The full-scale output current range of the AD9878 is 4 mA to 20 mA. Full-scale output currents outside of this range will degrade SFDR performance. SFDR is also slightly affected by output matching; that is, the two outputs should be terminated equally for best SFDR performance. The output load should be located as close as possible to the AD9878 package to minimize stray capacitance and inductance. The load may be a simple resistor to ground, an op amp current-to-voltage converter, or a transformer-coupled circuit. It is best not to attempt to directly drive highly reactive loads, such as an LC filter. Driving an LC filter without a transformer requires that the filter be doubly terminated for best performance; that is, the filter input and output should both be resistively terminated with the appropriate values. The parallel combination of the two terminations will determine the load that the AD9878 sees for signals within the filter pass band. For example, a 50 terminated input/output low-pass filter will look like a 25 load to the AD9878. The output compliance voltage of the AD9878 is -0.5 V to +1.5 V. Any signal developed at the DAC output should not exceed +1.5 V; otherwise signal distortion will result. Furthermore, the signal may extend below ground as much as 0.5 V without damage or signal distortion. The AD9878 true and complement outputs can be differentially combined for common-mode rejection using a broadband 1:1 transformer. Using a grounded center tap results in signals at the AD9878 DAC output pins that are symmetrical about ground. As previously mentioned, by differentially combining the two signals, the user can provide some degree of common-mode signal rejection. A differential combiner might consist of a transformer or an op amp. The object is to combine or amplify only the difference between two signals and to reject any common--usually undesirable--characteristic, such as 60 Hz hum or clock feedthrough that is equally present on both individual signals.
AD9878
DAC Tx CA LOW-PASS FILTER 3 CA_EN CA_DATA CA_CLK VARIABLE GAIN CABLE DRIVER AMPLIFIER
03277- 0- 011
FS
Tx THROUGHPUT AND LATENCY
Data inputs affect the output fairly quickly but remain effective due to the AD9878's filter characteristics. Data transmit latency through the AD9878 is easiest to describe in terms of fSYSCLK clock cycles (4 x fMCLK). The numbers quoted are when an effect is first seen after an input value change. Latency of I/Q data entering the data assembler (AD9878 input) to the DAC output is 119 fSYSCLK clock cycles (29.75 fMCLK cycles). DC values applied to the data assembler input will take up to 176 fSYSCLK clock cycles (44 fMCLK cycles) to propagate and settle at the DAC output. Frequency hopping is accomplished via changing the PROFILE input pin. The time required to switch from one frequency to another is less than 232 fSYSCLK cycles (58.5 fMCLK cycles).
D/A CONVERTER
A 12-bit digital-to-analog converter (DAC) is used to convert the digitally processed waveform into an analog signal. The worst-case spurious signals due to the DAC are the harmonics of the fundamental signal and their aliases (see the Analog Devices DDS Tutorial at www.analog.com/dds). The conversion process will produce aliased components of the fundamental signal at n x fSYSCLK fCARRIER (n = 1, 2, 3). These are typically filtered with an external RLC filter at the DAC output. It is important for this analog filter to have a sufficiently flat gain and linear phase response across the bandwidth of interest so as to avoid modulation impairments. A relatively inexpensive seventh order elliptical low-pass filter is sufficient to suppress the aliased components for HFC network applications. The AD9878 provides true and complement current outputs. The full-scale output current is set by the RSET resistor at Pin 49 and the DAC Gain register. Assuming maximum DAC gain, the value of RSET for a particular full-scale IOUT is determined using the equation:
AD832x
75
RSET = 32 VDACRSET/IOUT = 39.4/IOUT
For example, if a full-scale output current of 20 mA is desired,
Rev. 0 | Page 20 of 36
Figure 26. Cable Amplifier Connection
AD9878
Connecting the AD9878 true and complement outputs to the differential inputs of the programmable gain cable drivers AD8321/AD8323 or AD8322/AD8327 (see Figure 26) provides an optimized solution for the standard compliant cable modem upstream channel. The cable driver's gain can be programmed through a direct 3-wire interface using the AD9878's profile registers. with the current profile to the AD832x whenever the selected AD9878 cable driver amplifier gain setting is changed. Once a new stable gain value has been detected (48 to 64 MCLK cycles after initiation) data write starts with CA_EN going low. The AD9878 will always finish a write sequence to the cable driver amplifier once it is started. The logic controlling data transfers to the cable driver amplifier uses up to 200 MCLK cycles and has been designed to prevent erroneous write cycles from ever occurring.
PROGRAMMING THE AD8321/AD8323 OR AD8322/AD8327 CABLE DRIVER AMPLIFIER
Programming the gain of the AD832x family of cable driver amplifiers can be accomplished via the AD9878 cable amplifier control interface. Two 8-bit registers within the AD9878 (one per profile) store the gain value to be written to the serial 3-wire port. Typically, either the AD8321/AD8323 or AD8322/AD8327 variable gain cable amplifiers are connected to the chip's 3-wire cable amplifier interface. The Tx Gain Control Select bit in Register 0x0F changes the interpretation of the bits in Registers 0x13, 0x17, 0x1B, and 0x1F. See Figure 27 and Cable Driver Gain Control Register description.
8 tMCLK CA ENABLE CA_CLK CA_DATA MSB LSB
03277- 0- 012
OSCIN CLOCK MULTIPLIER
The AD9878 can accept either an input clock into the OSCIN pin or a fundamental mode crystal across the OSCIN and XTAL pins as the device's main clock source. The internal PLL then generates the fSYSCLK signal from which all other internal signals are derived. The DAC uses fSYSCLK as its sampling clock. For DDS applications, the carrier is typically limited to about 30% of fSYSCLK. For a 65 MHz carrier, the system clock required is above 216 MHz. The OSCIN multiplier function maintains clock integrity as evidenced by the AD9878 system's excellent phase noise characteristics and low clock-related spur in the output spectrum. External loop filter components consisting of a series resistor (1.3 k) and capacitor (0.01 F) provide the compensation zero for the OSCIN multiplier PLL loop. The overall loop performance has been optimized for these component values.
4 tMCLK 8 tMCLK 4 tMCLK
8 tMCLK
Figure 27. Cable Amplifier Interface Timing
CLOCK AND OSCILLATOR CIRCUITRY
The AD9878's internal oscillator generates all sampling clocks from a simple, low cost, parallel resonance, fundamental frequency quartz crystal. Figure 28 shows how the quartz crystal is connected between OSCIN (Pin 61) and XTAL (Pin 60) with parallel resonant load capacitors as specified by the crystal manufacturer. The internal oscillator circuitry can also be overdriven by a TTL level clock applied to OSCIN with XTAL left unconnected.
Data transfers to the programmable gain cable driver amplifier are initiated by four conditions: 1. Power-Up and Hardware Reset--Upon initial power-up and every hardware reset, the AD9878 clears the contents of the Gain Control registers to 0, which defines the lowest gain setting of the AD832x. Thus, the AD9878 writes all 0s out of the 3-wire cable amplifier control interface. 2. Software Reset--Writing a 1 to Bit 5 of Address 0x00 initiates a software reset. On a software reset, the AD9878 clears the contents of the Gain Control registers to 0 for the lowest gain and sets the Profile Select to 0. The AD9878 writes all 0s out of the 3-wire cable amplifier control interface if the gain was on a different setting (different from 0) before. 3. Change in Profile Selection--The AD9878 samples the PROFILE input pin together with the two Profile Select bits and writes to the AD832x Gain Control registers when a change in profile and gain is determined. The data written to the cable driver amplifier comes from the AD9878 Gain Control register associated with the current profile. 4. Write to the AD9878 Cable Driver Amplifier Control Registers--The AD9878 will write gain control data associated
fOSCIN = fMCLK x M
An internal phase-locked loop (PLL) generates the DAC sampling frequency, fSYSCLK, by multiplying the OSCIN frequency by M. The MCLK signal (Pin 23), fMCLK, is derived by dividing fSYSCLK by 4.
fSYSCLK = fOSCIN x M fMCLK = fOSCIN x M/4
An external PLL loop filter (Pin 57) consisting of a series resistor and ceramic capacitor (Figure 28: R1 = 1.3 k, C12 = 0.01 F) is required for stability of the PLL. Also, a shield surrounding these components is recommended to minimize external noise coupling into the PLL's voltage controlled oscillator input (guard trace connected to AVDDPLL).
Rev. 0 | Page 21 of 36
AD9878
Figure 22 shows that ADCs are either sampled directly by a low jitter clock at OSCIN or by a clock that is derived from the PLL output. Operating modes can be selected in Register 8. Sampling the ADCs directly with the OSCIN clock requires MCLK programmed to be twice the OSCIN frequency.
PROGRAMMABLE CLOCK OUTPUT REFCLK
The AD9878 provides an auxiliary output clock on Pin 69, REFCLK. The value of the MCLK divider bit field, R, determines its output frequency as shown in the equations
fREFCLK = fMCLK/R, for R = 2 to 63 fREFCLK = fOSCIN, for R = 0
In its default setting (0x00 in Register 1), the REFCLK pin provides a buffered output of fOSCIN.
CP2 10F C4 C5 0.1F 0.1F C6 0.1F
CP1 10F C1 C2 0.1F 0.1F C3 0.1F CP1 10F
REFB12A
REFB12B
REFT12A
REFT12B
VIDEO IN
AGND10
AVDD10
IF12A+
IF12B+
IF12A-
IF12B-
AGND
AGND
AGND
AGND
AGND
AGND
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
DRGND 1 DRVDD 2 (MSB) IF12(11) 3 IF12(10) 4 IF12(9) 5 IF12(8) 6 IF12(7) 7 IF12(6) 8 IF12(5) 9 IF12(4) 10 IF12(3) 11 IF12(2) 12 IF12(1) 13 IF12(0) 14 (MSB) IF10(4) 15 IF10(3) 16 IF10(2) 17 IF10(1) 18 IF10(0) 19 RxSYNC 20 DRGND 21 DRVDD 22 MCLK 23 DVDD 24 DGND 25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
AGND
AVDD
AVDD
AVDD
AVDD
AVDD
IF10+
IF10-
C1 C2 0.1F 0.1F
C3 0.1F
76 75 74 73 72 71 70 69 68 67 66
REFT10 REFB10 AGND10 AVDD10 DRVDD DRGND REFCLK SIGDELT FLAD(0) FLAG(1) CA_EN CA_DATA CA_CLK DVDDOSC OSCIN XTAL DGNDOSC AGNDPLL PLLFILT AVDDPLL DVDDPLL DGNDPLL AVDDTx Tx+ Tx- C12 R1 1.3k 0.01F GUARD TRACE C11 20pF C10 20pF
AD9878
TOP VIEW (Not to Scale)
65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
TxIQ(4)
TxIQ(3)
TxIQ(2)
TxIQ(1)
TxSYNC
TxIQ(0)
RESET
PROFILE
SDIO
(MSB) TxIQ(5)
REFIO
DVDD
DVDD
DGND
DGND
DVDD
DGND
SCLK
SDO
CS
DGNDTx
FSADJ
C13 0.1F
RSET 4.02
03277- 0- 013
Figure 28. Basic Connection Diagram
Rev. 0 | Page 22 of 36
AGNDTx
DVDDTx
PWRDN
AD9878
RESET AND TRANSMIT POWER-DOWN
POWER-UP SEQUENCE
On initial power-up, the RESET pin should be held low until the power supply is stable (see Figure 29). Once RESET is deasserted, the AD9878 can be programmed over the serial port. The on-chip PLL requires a maximum of 1 ms after the rising edge of RESET or a change of the multiplier factor (M) to completely settle. It is recommended that the PWRDN pin be held low during the reset and PLL settling time. Changes to ADC Clock Select (Register 0x08) or Sys Clock Divider N (Register 0x01) should be programmed before the rising edge of PWRDN. Once the PLL is frequency locked and after the PWRDN pin is brought high, transmit data can be sent reliably. If the PWRDN pin cannot be held low throughout the reset and PLL settling time period, then the Power-Down Digital Tx bit or the PWRDN pin should be pulsed after the PLL has settled. This will ensure correct transmit filter initialization.
VS
000h
Figure 30). This avoids unintended DAC output samples caused by the transmit path latency and filter settling time. Software Power-Down Digital Tx (Bit 5 in Register 0x02) is functionally equivalent to the hardware PWRDN pin and takes effect immediately after the last register bit has been written over the serial port.
PWRDN 5MCLK MIN. 20 NULL SYMBOLS TxIQ 0 0 0 0 DATA SYMBOLS 20 NULL SYMBOLS 0 0 0 0
TxSYNC
03277-0-015
Figure 30. Timing Sequence to Flush Tx Data Path
SIGMA-DELTA OUTPUTS
The AD9878 contains an on-chip sigma-delta output that provides a digital logic bit stream with an average duty cycle that varies between 0% and (4095/4096)%, depending on the programmed code, as shown in Figure 31.
8 tMCLK 4096 x 8 tMCLK
RESET 1ms MIN.
001h 002h
PWRDN
5MCLK MIN.
03277- 0- 014
800h FFFh 4096 x 8 tMCLK
Figure 29. Power-Up Sequence for Tx Data Path
RESET
To initiate hardware reset, the RESET pin should be held low for at least 100 ns. All internally generated clocks except OSCOUT stop during reset. The rising edge of RESET resets the PLL clock multiplier and reinitializes the programmable registers to their default values. The same sequence as described above in the Power-Up Sequence section should be followed after a reset or change in M. A software reset (writing a 1 into Bit 5 of Register 0x00) is functionally equivalent to the hardware reset but does not force Register 0x00 to its default value.
8 tMCLK
03277- 0- 016
Figure 31. Sigma-Delta Output Signals
This bit stream can be low-pass filtered to generate a programmable dc voltage of:
VDC = [(Sigma-Delta Code/4096) x VH]+ VL
where:
VH = VDRVDD - 0.6 V VL = 0.4 V
In cable modem set-top box applications, the output can be used to control external variable gain amplifiers or RF tuners. A simple single-pole RC low-pass filter provides sufficient filtering (see Figure 32).
TRANSMIT POWER-DOWN
A low level on the PWRDN pin stops all clocks linked to the digital transmit data path and resets the CIC filter. Deasserting PWRDN reactivates all clocks. The CIC filter is held in a reset state for 80 MCLK cycles after the rising edge of PWRDN to allow for flushing of the half-band filters with new input data. Transmit data bursts should be padded with at least 20 symbols of null data directly before the PWRDN pin is deasserted. Immediately after the PWRDN pin is deasserted, the transmit burst should start with a minimum of 20 null data symbols (see
Rev. 0 | Page 23 of 36
AD9878
AD9878
CONTROL WORD MCLK /8 12 DAC - R C DC (VL TO VH)
INPUT SIGNAL RANGE AND DIGITAL OUTPUT CODES
The IF ADCs have differential analog inputs labeled IF+ and IF-. The signal input, VAIN, is the voltage difference between the two input pins, VAIN = VIF+ - VIF-. The full-scale input voltage range is determined by the internal reference voltages, REFT and REFB, which define the top and bottom of the scale. The peak input voltage to the ADC is the difference between REFT and REFB, which is 1 VPD. This results in the ADC full scale input voltage range of 2 VPPD. The digital output code is straight binary and is illustrated in Table 6.
TYPICAL: R = 50k C = 0.01F f-3dB = 1/(2RC) = 318Hz
03277- 0-017
Figure 32. Sigma-Delta RC Filter
In more demanding applications where additional gain, level shift, or drive capability is required, a first or second order active filter might be considered (see Figure 33).
C R1
Table 6
IF12[11:0] 111...111 111...111 111...110 ... 100...001 100...000 011...111 ... 000...001 000...000 000...000 Input Signal Voltage VAIN +1.0 V VAIN = +1.0 V - (1 LSB) VAIN = +1.0 V - (2 LSB) ... VAIN = 0 V + 1 LSB VAIN = 0.0 V VAIN = 0 V - 1 LSB ... VAIN = -1.0 V + (2 LSB) VAIN = -1.0 V VAIN < -1.0 V
AD9878
SIGMA-DELTA - VSD R C
R
VOUT R VOFFSET OP250
VOUT = (VSD + VOFFSET) (1 + R/R1)/2 TYPICAL: R = 50k C = 0.01F f-3dB = 1/(2RC) = 318Hz
03277- 0- 018
Figure 33. Sigma-Delta Active Filter with Gain and Offset
DRIVING THE INPUT
RECEIVE PATH (Rx)
The AD9878 includes three high speed, high performance ADCs. The 10-bit and dual 12-bit direct IF ADCs deliver excellent undersampling performance with input frequencies as high as 70 MHz. The sampling rate can be as high as 33 MSPS. The ADC sampling frequency can be derived directly from the OSCIN signal or from the on-chip OSCIN multiplier. For highest dynamic performance, it is recommended to choose an OSCIN frequency that can be directly used as the ADC sampling clock. Digital 12-bit ADC outputs are multiplexed to one 12-bit bus, clocked by a frequency (fMCLK) of four times the sampling rate. The IF ADCs use a multiplexer to a 12-bit interface with an output word rate of fMCLK.
The IF ADCs have differential switched capacitor sample-andhold amplifier (SHA) inputs. The nominal differential input impedance is 4.0 k||3 pF. This impedance can be used as the effective termination impedance when calculating filter transfer characteristics and voltage signal attenuation from nonzero source impedances. It should be noted, however, that for best performance, additional requirements must be met by the signal source. The SHA has input capacitors that must be recharged each time the input is sampled. This results in a dynamic input current at the device input, and demands that the source has low (<50 ) output impedance at frequencies up to the ADC sampling frequency. Also, the source must have settling to better than 0.1% in <1/2 ADC CLK period. Another consideration for getting the best performance from the ADC inputs is the dc biasing of the input signal. Ideally, the signal should be biased to a dc level equal to the midpoint of the ADC reference voltages, REFT12 and REFB12. Nominally, this level will be 1.2 V. When ac-coupled, the ADC inputs will selfbias to this voltage and require no additional input circuitry. Figure 34 illustrates a recommended circuit that eases the burden on the signal source by isolating its output from the ADC input. The 33 series termination resistors isolate the amplifier outputs from any capacitive load, which typically improves settling time. The series capacitors provide ac signal coupling which ensures that the ADC inputs operate at the
IF10 AND IF12 ADC OPERATION
The IF10 and IF12 ADCs have a common architecture and share many of the same characteristics from an applications standpoint. Most of the information in the section below will be applicable to both IF ADCs. Differences, where they exist, will be highlighted.
Rev. 0 | Page 24 of 36
AD9878
optimal dc bias voltage. The shunt capacitor sources the dynamic currents required to charge the SHA input capacitors, removing this requirement from the ADC buffer. The values of CC and CS should be calculated to get the correct HPF and LPF corner frequencies.
33 VS 33 CC AINP CC CS AINN
03277- 0- 019
of the reference pins REFT and REFB. External references may be necessary for systems that require high accuracy gain matching between ADCs or for improvements in temperature drift and noise characteristics. External references REFT and REFB need to be centered at AVDD/2 with offset voltages as specified: REFT-10, -12: AVDD/2 + 0.5 V REFB-10, -12: AVDD/2 - 0.5 V A differential level of 1 V between the reference pins results in a 2 V p-p ADC input level AIN. Internal reference sources can be powered down when external references are used (Register Address 0x02).
Figure 34. Simple ADC Drive Configuration
RECEIVE TIMING
The AD9878 sends multiplexed data to the IF10 and IF12 outputs on every rising edge of MCLK. RxSYNC frames the start of each IF10 data symbol. 10-bit and 12-bit ADCs are completely read on every second MCLK cycle. RxSYNC is high for every second 10-bit ADC data (if 10-bit ADC is not in power-down mode).The Rx timing diagram is shown in Figure 35.
tEE
OSCOUT M/N = 2
VIDEO INPUT
For sampling video-type waveforms, such as NTSC and PAL signals, the Video Input channel provides black level clamping. Figure 36 shows the circuit configuration for using the Video Channel input (Pin 98). An external blocking capacitor is used with the on-chip video clamp circuit to level-shift the input signal to a desired reference point. The clamp circuit automatically senses the most negative portion of the input signal, and adjusts the voltage across the input capacitor. This forces the black level of the input signal to be equal to the value programmed into the Clamp Level register (Register Address 0x07).Video Input can be multiplexed to the IF12A ADC (default) or to the IF12B ADC by programming Register Address 0x03.
CLAMP LEVEL +FS/2
tMD
tOD
MCLK
IF10 DATA RxSYNC IF12 DATA
IF10[9:5] IF10[4:0] IF10[9:5] IF10[4:0] IF10[9:5] IF10[4:0]
IF12A
IF12B
IF12B
IF12B
IF12A
IF12B
AD9878
CLAMP LEVEL 12 ADC 2mA BUFER
Rx PORT TIMING (DEFAULT MODE: MUXED IF12 ADC DATA) tEE
OSCOUT M/N = 2
VIDEO INPUT 0.1F
CLAMP LEVEL
-
+ LPF
DAC OFFSET
03277- 0- 021
tMD
tOD
MCLK
IF10[9:5] IF10[4:0] IF10[9:5] IF10[4:0] IF10[9:5] IF10[4:0]
Figure 36. Video Clamp Circuit Input
IF10 DATA RxSYNC IF DATA
PCB DESIGN CONSIDERATIONS
Although the AD9878 is a mixed-signal device, the part should be treated as an analog component. The digital circuitry onchip has been specially designed to minimize the impact that the digital switching noise will have on the operation of the analog circuits. Following the power, grounding, and layout recommendations in this section will help the user get the best performance from the MxFE.
IF12A OR IF12B
IF12A OR IF12B
IF12A OR IF12B
Rx PORT TIMING (OUTPUT DATA FROM ONLY ONE IF12 ADC)
03277- 0- 020
Figure 35. Rx Port Timing
ADC VOLTAGE REFERENCES
The AD9878 has three independent internal references for its 10-bit and 12-bit ADCs. Both 12-bit and 10-bit ADCs are designed for 2 V p-p input voltages with each of them having its own internal reference. Figure 28 shows the proper connections
COMPONENT PLACEMENT
If the three following guidelines of component placement are followed, chances for getting the best performance from the MxFE are greatly increased.
Rev. 0 | Page 25 of 36
AD9878
* First, manage the path of return currents flowing in the ground plane so that high frequency switching currents from the digital circuits do not flow on the ground plane under the MxFE or analog circuits. * Second, keep noisy digital signal paths and sensitive receive signal paths as short as possible. * Third, keep digital (noise generating) and analog (noise susceptible) circuits as far away from each other as possible. In order to best manage the return currents, pure digital circuits that generate high switching currents should be closest to the power supply entry. This will keep the highest frequency return current paths short, and prevent them from traveling over the sensitive MxFE and analog portions of the ground plane. Also, these circuits should be generously bypassed at each device to further reduce the high frequency ground currents. The MxFE should be placed adjacent to the digital circuits, such that the ground return currents from the digital sections will not flow in the ground plane under the MxFE. The analog circuits should be placed furthest from the power supply. The AD9878 has several pins that are used to decouple sensitive internal nodes. These pins are REFIO, REFB12A, REFT12A, REFB12B, REFT12B, REFB10, and REFT10. The decoupling capacitors connected to these points should have low ESR and ESL. The capacitors should be placed as close to the MxFE as possible and be connected directly to the analog ground plane. The resistor connected to the FSADJ pin and the RC network connected to the PLLFILT pin should also be placed close to the device and connected directly to the analog ground plane. power plane. The AVDD and DVDD power planes may be fed from the same low noise voltage source; however, they should be decoupled from each other to prevent the noise generated in the DVDD portion of the MxFE from corrupting the AVDD supply. This can be done by using ferrite beads between the voltage source and DVDD, and between the source and AVDD. Both DVDD and AVDD should have a low ESR, bulk decoupling capacitor on the MxFE side of the ferrite as well as low ESR, ESL decoupling capacitors on each supply pin (i.e., the AD9878 requires 17 power supply decoupling capacitors). The decoupling capacitors should be placed as close to the MxFE supply pins as possible. An example of proper decoupling is shown in the AD9878 evaluation board schematic (Figure 38 and Figure 39).
GROUND PLANES
In general, if the component placing guidelines discussed earlier can be implemented, it is best to have at least one continuous ground plane for the entire board. All ground connections should be made as short as possible. This will result in the lowest impedance return paths and the quietest ground connections. If the components cannot be placed in a manner that would keep the high frequency ground currents from traversing under the MxFE and analog components, it may be necessary to put current steering channels into the ground plane to route the high frequency currents around these sensitive areas. These current steering channels should be made only when and where necessary.
SIGNAL ROUTING
The digital Rx and Tx signal paths should be kept as short as possible. Also, these traces should have a controlled impedance of about 50 . This will prevent poor signal integrity and the high currents that can occur during undershoot or overshoot caused by ringing. If the signal traces cannot be kept shorter than about 1.5 inches, then series termination resistors (33 to 47 ) should be placed close to all signal sources. It is a good idea to series terminate all clock signals at their source regardless of trace length. The receive signals are the most sensitive signals on the entire board. Careful routing of these signals is essential for good receive path performance. The IF+/IF- signals form a differential pair and should be routed together as a pair. By keeping the traces adjacent to each other, noise coupled onto the signals will appear as common mode and will be largely rejected by the MxFE receive input. Keeping the driving point impedance of the receive signal low and placing any low-pass filtering of the signals close to the MxFE will further reduce the possibility of noise corrupting these signals.
POWER PLANES AND DECOUPLING
The AD9878 evaluation board (Figure 38 and Figure 39) demonstrates a good power supply distribution and decoupling strategy. The board has four layers: two signal layers, one ground plane, and one power plane. The power plane is split into a 3 VDD section that is used for the 3 V digital logic circuits, a DVDD section that is used to supply the digital supply pins of the AD9878, an AVDD section that is used to supply the analog supply pins of the AD9878, and a VANLG section that supplies the higher voltage analog components on the board. The 3 VDD section will typically have the highest frequency currents on the power plane and should be kept the furthest from the MxFE and analog sections of the board. The DVDD portion of the plane carries the current used to power the digital portion of the MxFE to the device. This should be treated similarly to the 3 VDD power plane and be kept from going underneath the MxFE or analog components. The MxFE should largely sit above the AVDD portion of the
Rev. 0 | Page 26 of 36
AD9878
PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIOINS
REFB12A REFB12B REFT12A REFT12B VIDEO IN AGND10 AVDD10 IF12A+ IF12B+ IF12A- IF12B- AGND AGND AGND AGND AGND AGND
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
DRGND 1 DRVDD 2 IF12(11) 3 IF12(10) 4 IF12(9) 5 IF12(8) 6 IF12(7) 7 IF12(6) 8 IF12(5) 9 IF12(4) 10 IF12(3) 11 IF12(2) 12 IF12(1) 13 IF12(0) 14 IF10(4) 15 IF10(3) 16 IF10(2) 17 IF10(1) 18 IF10(0) 19 RxSYNC 20 DRGND 21 DRVDD 22 MCLK 23 DVDD 24 DGND 25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
AGND
76 75 74 73 72 71 70 69 68 67 66
AVDD
AVDD
AVDD
AVDD
AVDD
IF10+
IF10-
REFT10 REFB10 AGND10 AVDD10 DRVDD DRGND REFCLK SIGDELT FLAD(0) FLAG(1) CA_EN CA_DATA CA_CLK DVDDOSC OSCIN XTAL DGNDOSC AGNDPLL PLLFILT AVDDPLL DVDDPLL DGNDPLL AVDDTx Tx+ Tx-
AD9878 100-LEAD LQFP
TOP VIEW (Not to Scale)
65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
PROFILE
TxIQ(5)
TxIQ(4)
TxIQ(3)
TxIQ(2)
TxIQ(1)
TxSYNC
TxIQ(0)
RESET
DVDD
DVDD
DVDD
SCLK
SDIO
SDO
CS
REFIO
DGNDTx
FSADJ
AGNDTx
DVDDTx
PWRDN
DGND
DGND
DGND
03277- 0- 002
Figure 37. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. 1, 21, 70 2, 22, 71 3-14 15-19 20 23 24, 35, 39 25, 34, 36, 40 26 27:32 37 38 41 42 43 44 45 46 47 48 49 Mnemonic DRGND DRVDD IF12[11:0] IF10[4:0] RxSYNC MCLK DVDD DGND TxSYNC TxIQ[5:0] PROFILE RESET SCLK CS SDIO SDO DGNDTx DVDDTx PWRDN REFIO FSADJ Pin Function Pin Driver Digital Ground Pin Driver Digital 3.3 V Supply 12-Bit ADCs Digital Ouput 10-Bit ADC Digital Ouput Sync Output, 10- and 12-Bit ADCs Master Clock Output Digital 3.3 V Supply Digital Ground Sync Input for Transmit Port Digital Input for Transmit Port Profile Selection Input Chip Reset Input SPORT Clock SPORT Chip Select SPORT Data I/O SPORT Data Output Tx Path Digital Ground Tx Path Digital 3.3 V Supply Power-Down Transmit Path TxDAC Decoupling (to AGND) DAC Output Adjust (External Res.)
Rev. 0 | Page 27 of 36
AD9878
Pin No. 50 51, 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66, 67 68 69 72, 80 73, 79 74 75 76, 81, 86, 89, 94, 97, 99 77, 78 82, 85, 90, 93, 100 83 84 87, 88 91 92 95, 96 98 Mnemonic AGNDTx Tx-, Tx+ AVDDTx DGNDPLL DVDDPLL AVDDPLL PLLFILT AGNDPLL DGNDOSC XTAL OSCIN DVDDOSC CA_CLK CA_DATA CA_EN FLAG[2:1] SIGDELT REFCLK AVDD10 AGND10 REFB10 REFT10 AGND IF10-, IF10+ AVDD REFB12B REFT12B IF12B-, IF12B+ REFB12A REFT12A IF12A-, IF12A+ VIDEO IN Pin Function Tx Path Analog Ground Tx Path Complementary Outputs Tx Path Analog 3.3 V Supply PLL Digital Ground PLL Digital 3.3 V Supply PLL Analog 3.3 V Supply PLL Loop Filter Connection PLL Analog Ground Oscillator Digital Ground Crystal Oscillator Inverted Output Oscillator Clock Input Oscillator Digital 3.3 V Supply Serial Clock to Cable Driver Serial Data to Cable Driver Serial Enable to Cable Driver Programmable Flag Outputs Sigma-Delta DAC Output Reference Clock Output 10-Bit ADC Analog 3.3 V Supply 10-Bit ADC Analog Ground 10-Bit ADC Ref Decoupling Node 10-Bit ADC Ref Decoupling Node 12-Bit ADC Analog Ground Differential Input to 10-bit ADC 12-Bit ADC Analog 3.3 V Supply ADC12B Ref Decoupling Node ADC12B Ref Decoupling Node Differential Input to ADC12B ADC12A Ref Decoupling Node ADC12A Ref Decoupling Node Differential Input to ADC12A Video Clamp Input
Rev. 0 | Page 28 of 36
5V_AD8328
RC0805
5V_AD8328
R28 1K 1 2 3 4 5 6
C117
CC0603
DUTY CYCLE V_CLK
RC0805
R6
AGND;3,4,5
CC0603
TX_OUT AD8328
SMAEDGE
500 C83 C84
BCASE CC0805 16V CC0805 10UF 0.1UF 0.1UF CC0603
C110
POT1
J8
2 C116 0.1UF 7 8 CAENABLE CADATA CACLK 2 P1 5S TOKOB5F C72
CC0805
1 43.3
RC0805
R39 0.1UF 4 3
T6
C115
0.1UF
AD8328 20 GND5 GND 19 VCC1 VCC 18 TXEN GND1 17 RAMP GND2
OSC_IN_CLK
CW AGND;3 V_CLK;5 U13
10K R5
4
RC0805 RC0805
AGND;3,4,5
SMA200UP
0.1UF
NC7SZ04
CC0805
J3
R40 33 86.6 TX+ TX_OUT 75
RC0805
C19
2
16 VOUT+ U4 VIN+ 15 VOUTVIN14 BYP GND3 13 NC DATAEN 12 SLEEP 11 GND4 SDATA 9 CLK 10
0.1UF EXT_CLK JP1 OSCIN
CA_SLEEP
RC0805
R9 R7
RC0805
49.9 500 3
SMAEDGE
18PF
AGND;3,4,5
CC0603
C18 C23 R11
RC0805
1 TRANSF L16 18PF 33PF
CC0805 CC0805
18PF
CC0805
C17 XTAL
CC0603
2
Y1 VAL
J4
1 2 5 6
1 18PF C58 75 R36 220
LC1210 RC0805 RC0805
DIP06RCUP
2 AB3 AD8328 JP8 L15 R38
CC0603
C24 0.1UF 1 TRANSF L13 L14
LC1210
2 AB3 AD8328 JP7
CC0603
0.1UF IF10+ AVDDTX DVDDPLLOSC
CC0603 RC0805
C111 33 10K
RC0805
R31
CC0805
1
LC1210 LC1210
TRANSF 220 220
0.01UF C114
59 R37 0.01UF C113
2 TXC20 C57 220
CC0805
0.1UF 37.5 R12 37.5
RC0805
3
T1
4
IF-10
DIP06RCUP
8138+ JP30 VCML
CC0603 CC0603
U1 RESET C21
CC0603
AGND;3,4,5 1 2 3 4
CC0805
AD8138 2 TRANSF 3 BA1 JP31
6 5
SMAEDGE
1 C22
CC0603
VCC RESET 2 GND
2 3
DRVDD
CC0603
J15
R33 C69CC0603 0.01UF
RC0805
1 C66 C16 51 52 53 54 55 IF10TP4
CC0603
R10 50
2 49.9 T5 20PF TRANSF R32 C112 33 C15
RC0805 RC0805
R4 TXTX+ AVDDTX DGNDPLL DVDDPLL AVDDPLL PLLFILT AGNDPLL DGNDOSC XTAL OSCIN DVDDOSC CACLK CADATA CAEN FLAG2 FLAG1 SIGDELT REFCLK 68 69 DRVDD 70 DRGND DRVDD AVDD10 71 72 73 74 75 76 77 AGND10 REFB10 REFT10 AGND1 IF10BIF10B+ 78 79 80 AGND10-A FSADJ
1.3K
RC0805
C108
0.1UF 0.1UF
U2 AD9878LQFP AGNDTX
SW1
0.1UF 0.1UF PWRDOWN DVDDTX 1
4 3 AGND;5 RESET
ADM1818-10ART
C1 0.1UF
8138CC0603
AD81381
JP32 AB3 2 0.1UF WHT 100K R3 TP3 TP1 WHT 62 63 64 65 66 67 WHT 61 TP2 WHT WHT WHT WHT CACLK CADATA CAENABLE 0.1UF IF12B+
CC0603 RC0805
49 REFIO 48 PWRDN 47 DVDDTX 46 DGNDTX
SDO,SDIO,CS,SCLK SDO SDIO CS
R2 R3 R4 R5 R6 R7 R8 R9
56 57 58 XTAL OSCIN 59 60
DRVDD PWRDOWN
SCLK DVDD
J2
1 RCOM R1 2 22 3 4 5 6 7 8 9 RP1 10
RC0805
0.01UF
TP15
TP6
TP5
RIBBON R29 10K 25 23 JP9 PROFILE1 TXIQ0 TXIQ1 TXIQ2 TXIQ3 TXIQ4 TXIQ5 TXSYNC 21 19 17 26 24 22 20 18
C101 33 TRANSF JP24 C98 C11 C12
CC0603 CC0603 CC0603
R26
FLAG2 FLAG1 SDELTA0 REFCLK
IF-12B
DIP06RCUP
8138+
AGND;3,4,5 1 6
AD8138 2 3 BA1 JP25 C13 C14
BCASE
J13
R27
2 3 5
1 16V 0.1UF VCML
CC0805
2 49.9 T3 10UF IF10R25 33 C6 C7
CC0603 CC0603
9 7 5 3 1
10 8 6 4 2
4
0.1UF
0.1UF
8138-
JP26 1 AB3 AD8138 2 TRANSF
CC0603
MCLK DRVDD RXSYNC
523
RC0805
499 2
RC0805
J11
R20 49.9
1 2 3
6 5 4
JP22 VCML C92 T2
CC0805
2
33OHM
RC07CUP
A_BUFFC97
CC0805
BCASE
R1 75OHM 20PF AD81381 JP23 TRANSF AB3 2
CC0603 RC0805
C96 16V 10UF 0.1UF
RC0805
C95 47PF CC1206 33 R21 8138-
R19 0.1UF C94 33 IF12A-
CC0603
Figure 38. AD9878 Evaluation PCB Schematic (page1)
0.1UF C102 IF12B-
RC0805
IF10+
10V C8
BCASE
C9
CC0603
0.1UF JP4 IF12B-
0.1UF
0.1UF 10UF
81 82 83 84 85 86 87
AVDD10-A AGND2 AVDD1 REFB12B REFT12B AVDD2 AGND3 IF12B88 89 IF12B+ AGND4
IFB0 IFB1 IFB2 IFB3 IFB4 IF0 IF1
IF12B+ R16 C2
CC0603
C90
CC0805
C87
CC0805
C3
CC0603
C91 10UF 16V R15 0.1UF VCML 8138+ 33 C86 0.1UF
CC0603 RC0805
C5 0.1UF 0.1UF 10V C4 BCASE 10UF
CC0603
IF2 IF3 0.1UF 90 91 92 AVDD3 REFB12A REFT12A IF4 IF5 IF6 IF7 93 94 95 96 AVDD4 AGND5 IF12AIF12A+ IF8 IF9 IF10 IFB[0:4]
BCASE
5.11K
0.1UF 10K R14
RC0805
AGND;3,4,5
AD8138 R17
RC0805
A_BUFF+
SMAEDGE
R18 499
J12
AD8138 5
VOVOC VO+ 2
1
RC0805
2
499
6
RC0805
8 4 C88
AGND;3,4,5
SMAEDGE
+IN VEE
R13 33
R24 49.9
U9
IF12A+ VIDEO IN
AGND;3,4,5
SMAEDGE
97 98 99 AVDD C10 100 0.1UF R2
AGND6 VIDEOIN AGND7 AVDD5
IF11 IF[0:11]
1 R22
CC1206
-IN
VCC
3
R23 47PF IF-12A 1
JP21 AD8138 2 TRANSF 3 BA1
DIP06RCUP
45 SDO 44 SDIO 43 CS 42 SCLK 41 DGND4 40 DVDD4 39 RESET 38 PROFILE 37 DGND3 36 DVDD3 35 DGND2 34 DVDD2 33 TXIQ0 32 TXIQ1 31 TXIQ2 30 TXIQ3 29 TXIQ4 28 TXIQ5 27 TXSYNC 26 DGND1 25 DVDD1 24 MCLK 23 DRVDD2 22 DRGND2 21 RXSYNC 20 IFB0 19 IFB1 18 IFB2 17 IFB3 16 IFB4 15 IF0 14 IF1 13 IF2 12 IF3 11 IF4 10 IF5 9 IF6 8 IF7 7 IF8 6 IF9 5 IF10 4 IF11 3 DRVDD1 2 DRGND1 1 1
HEADER RA RIBBON
15 13 11
RC0805
20PF
RC0805
J1
03277-0-038
RC0805
DIGITAL TRANSMIT
16 14 12
Rev. 0 | Page 29 of 36
RC0805 RC0805
SMAEDGE
AD9878
L17 VAL C93
CC0805
TP20 CLR
AD9878
LC1210
V_CLK
BCASE
C89 10UF 16V 0.1UF TP18 CLR
L7
VAL
LC1210
AVDD
C85 C76 C74
CC0603 CC0603 CC0603 CC0603
C62
CC0805
C71 0.1UF 1 3 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
MCLK AGND;3,4,5
SMAEDGE
C68 0.1UF 2 SCS SSCLK SSDIO SDOPC 0.1UF
C65
J5
RIBBON
BCASE
C59 10UF 16V 0.1UF 0.1UF TP17 CLR 0.1UF 0.1UF
CC0603 CC0603
P1
1 2 3 4 5 6 7 8
RJ45
L9
VAL
LC1210
AVDDTX
7 C75 9 11 13 15 17 19 21 23 25
CC0603
5
C64
CC0805 CC0603 CC0603 CC0603
C67 0.1UF TP16 CLR 0.1UF 0.1UF 0.1UF
C70
C73
BCASE
C61 10UF 16V 0.1UF VAL
3_3VA AVDDPLL
C63
CC0805
L8
LC1210
BCASE
9
10
11
12
C60 10UF 16V 0.1UF TP14 CLR 27 C81 31 33 35 37 VAL TP12 CLR 39 DVDD R8 CA_SLEEP R35
RC0603 CC0805
ABUFFA_BUFF29
L11
VAL
LC1210
BCASE
DIGITAL RECEIVE
16V 10UF C78 0.1UF
R34
1K
RC0603
1 2 100
RC0603
14 JP3 3 4 5 6 7 8 9 15 16 17 18 19 20 21 10 22
1
2 C80
CC0805 HDR040RA
ABUFF+ A_BUFF+
L10
LC1210
3 0.1UF 2 TP13 CLR 33
4
BCASE
5
C77 10UF 16V
J7
1
JP2
7 VAL
5V 5V_AD8328
C82
CC0805
AD8328
6
3
JP5 AB 2
12
24
1
BCASE
C79 10UF 16V 0.1UF
13
DEL_CLK
25
JP6 3 AB 2
DCN25RPT
J6
L1
VAL
TP19 CLR
16
15
14
13
12
11
CC0805
CC0603
CC0603
CC0603
C37
10 11 12 13 14 15 16 10 11 12 13 14 15 16 9 9
RP4 22
RP4 22
RP4 22
RP4 22
RP4 22
RP4 22
RP4 22
1
2
3
4
5
6
7
AGND;3 DBUFF5V;5
U3
2 4
8
RP4 22
BCASE
C25 10UF 16V 0.1UF 0.1UF
22 RP3 22 RP3 22 RP3 22 RP3 22 RP2 22 RP3 22 RP3 22 RP3 22 RP3 22 RP2 22 RP2 22 RP2
C31 0.1UF
C34 0.1UF
10
9
23
22
14
15
16
17
18
19
20
21
24
23
22
14
15
16
17
18
19
20
21
13
24
23
22
21
20
19
18
17
16
15
14
24
23
22
21
20
19
18
17
16
15
14
24
13
BCASE
CC0805
C32 C35 C38 CC0603 CC0603 0.1UF 0.1UF 0.1UF
CC0603
C39 0.1UF
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B0
B1
B2
B3
B4
B5
B6
B7
B0
B1
B2
B3
B4
B5
B6
OE
OE
OE
NC
NC
NC
GND3
GND3
GND3
NC
OE
B7
VCCB
VCCB
L4
VAL
TP8 CLR
LC1210
DVDDPLLOSC
U5
TSSOP24
VCCB
TSSOP24
TSSOP24
C43
CC0805 CC0603 CC0603 CC0603
74LVXC3245
74LVXC3245
74LVXC3245
C40 10UF 16V 0.1UF
T/R
VCCA
T/R
A7
A6
A5
A4
A3
A2
A1
A0
GND1
GND2
VCCA
T/R
A7
A6
A5
A4
A3
A2
A1
A0
GND1
GND2
A1
A2
A3
A4
A5
A6
A7
GND1
GND2
T/R
0.1UF 0.1UF TP9 CLR
0.1UF
A1
A2
A3
A4
74LVXC3245
BCASE
A5
A6
A7
GND1
VCCA
A0
VCCA
L3
VAL
U7
U8
1
2
10
9
8
7
6
5
4
3
11
12
1
2
10
9
8
7
6
5
4
3
11
12
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
C30
9 12 11 10
CC0805 CC0603
7
16
14
15
13
14
15
12
13
10
11
16
22
22
8
RP7
RP7
RP6
RP6
RP6
RP6
RP6
RP6
RP5
RP5
RP5
RP5
2
3
IFB3
IFB2
IFB1
LC1210
DBUFF3-5V
C45
CC0603
BCASE
IF11
IF10
C42 10UF 16V
CC0805
0.1UF VAL C44
CC0805 CC0603
C56 C54 C51 C48 CC0603 CC0603 CC0603 0.1UF 0.1UF 0.1UF 0.1UF
IF9
IF8
IF7
IF6
IF5
IF4
IF3
IF2
L5
RXSYNC
SDOPC
IF0
MCLK
SCLK
DBUFF5V
C47 C50 C55 C53 C100 CC0603 CC0603 CC0603 CC0603 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
IF[0:11]
2 AB3 JP13 1
SDIO
LC1210
CS
TP11 CLR
IF1
IFB0
IFB4
1
RP7
L6
VAL
TP10 CLR
8
4
BCASE
C41 10UF 16V 0.1UF
IFB[0:4]
DEL_CLK
RP6
RP6
RP5
RP5
RP5
RP5
22
RP7
C27 10UF 16V
22 22 22
0.1UF
6 7
C36 C33 CC0603 0.1UF 0.1UF
22
22
22
22
22
22
22
22
22
22
22
22
22
22
BCASE
6
5
12
LC1210
DVDDTX
DBUFF3-5V
A0
GND2
TSSOP24
C52
C49
C46
U6
VCCB
GND3
Figure 39. AD9878 Evaluation PCB Schematic (page2)
INVERT CLK
C26 10UF 16V
CC0603
0.1UF
13
13
Rev. 0 | Page 30 of 36
DVDD
C28
22 RP2 22 RP2 22 RP2 22 RP2 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
LC1210
L2
VAL
TP7 CLR
SDO
NC7SZ04
LC1210
DRVDD
DBUFF5V
C29
03277-0-039
PC PARALLEL PORT
DEL_CLK 11 23
8
3_3VD
L12
LC1210
1
9
2
4 5
1
2
3
4
6
8
3
5
7
1
AD9878
03277-0-040
Figure 40. AD9878 Evaluation PCB--Top Assembly
03277-0-041
Figure 41. AD9878 Evaluation PCB--Bottom Assembly
Rev. 0 | Page 31 of 36
AD9878
03277-0-042
Figure 42. AD9878 Evaluation PCB Layout--Top Layer
03277-0-043
Figure 43. AD9878 Evaluation PCB Layout--Bottom Layer
Rev. 0 | Page 32 of 36
AD9878
03277-0-044
Figure 44. AD9878 Evaluation PCB--Power Plane
Figure 45. AD9878 Evaluation PCB--Ground Plane
Rev. 0 | Page 33 of 36
AD9878
OUTLINE DIMENSIONS
1 6 .0 0 BSC SQ
1 .6 0 MAX 0 .7 5 0 .6 0 0 .4 5 SEATING PLANE TOP VIEW 12 TYP
100 1
1 4 .0 0 BSC SQ
76 75
PIN 1
1 .4 5 1 .4 0 1 .3 5
0 .1 5 0 .0 5
10 6 2
( PINS DOWN)
1 2 .0 0 REF
SEATING PLANE
0 .20 0 .09 7 3 .5 0 0 .0 8 MAX COPLANARITY
VIEW A
25 26 51 50
0 .5 0 BSC
VIEW A
ROTATED 9 0 CCW COMPLIANT TO JEDEC STANDARDS MS-0 2 6 BED
0 .27 0 .22 0 .17
Figure 46.
100-Lead Low Profile Quad FlapPackage [LQFP] (ST-100) Dimensions shown in millimeters
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Model AD9878BST
AD9878BSTRL
Temperature Range
-40C to +85C
-40C to +85C
Package Description 100-LQFP
100-LQFP
Package Option ST-100
ST-100
Rev. 0 | Page 34 of 36
AD9878
NOTES
Rev. 0 | Page 35 of 36
AD9878
NOTES
(c) 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. C03277-0-5/03(0)
Rev. 0 | Page 36 of 36
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